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| Fault Tolerant CAN - LDO Final Data Sheet 1 1.1 Overview Features TLE 6262 G * Standard fault tolerant differential CAN-transceiver (TLE6254 LS CAN cell) * Bus failure management * Low power mode management * CAN data transmission rate up to 125 kBaud * Low-dropout voltage regulator 5V 2% * Two Low Side Switches * Three High Side Switches * Power on and under-voltage reset generator * Vcc supervisor * Window watchdog * Programable time base * Integrated fail-safe mechanism * Standard 16 bit SPI-Interface * Wide input voltage and temperature range * Enhanced power P-DSO-Package Type TLE 6262 G Ordering Code on request P-DSO-28-6 Enhanced Power Package P-DSO-28-6 Description The TLE 6262 G is a monolithic integrated circuit in a P-DSO-28-6 package, which incorporates a failure tolerant low speed CAN-transceiver for differential mode data transmission, a low dropout voltage regulator for internal and external 5V supply as well as a 16 bit SPI interface to control and monitor the IC. Further there are integrated three high side switches, two low side switches, a window watchdog circuit and a reset circuit. Both, the window watchdog and reset function are referring to a time base that is programmable via an external resistor. The IC is designed to withstand the severe conditions of automotive applications. 1 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G 1.2 Pin Configuration (top view) CANH 1 RTH 2 RO 3 CANL 4 RTL 5 GND 6 GND 7 GND 8 GND 9 OUTH1 10 OUTL1 11 OUTL2 12 OUTH2 13 OUTH3 14 28 OSC 27 PWM 26 TxD 25 RxD 24 Vcc 23 GND 22 GND 21 GND 20 GND 19 CLK 18 DI 17 DO 16 CSN 15 Vs P-DSO-28-6 (enhanced power package) Figure 1 2 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G 1.3 Pin No. 1 2 3 4 5 Pin Definitions and Functions Symbol CANH RTH RO CANL RTL Function CAN-H bus line; HIGH in dominant state Termination input for CANH Reset output; open drain output; integrated pull up; active low CAN-L bus line; LOW in dominant state Termination input for CANL Ground; to reduce thermal resistance place cooling areas on PCB close to this pins. High side output 1; controlled via PWM input and/or SPI input, short circuit protected Low side output 1; SPI controlled, with active zener Low side output 2; SPI controlled, with active zener High side output 2; SPI controlled High side output 3; SPI controlled, in low power mode controlled by internal autotiming function if selected Power supply; block to GND directly at the IC with ceramic capacitor SPI interface chip select not; CSN is an active low input; serial communication is enabled by pulling the CSN terminal low; CSN input should only be transitioned when CLK is low; CSN has an internal active pull up and requires CMOS logic level inputs SPI interface data out; this tristate output transfers diagnosis data to the control device; the output will remain 3-stated unless the device is selected by a low on Chip-Select-Not (CSN); see table 3 for diagnosis protocol SPI interface data in; receives serial data from the control device; serial data transmitted to DI is a 16 bit control word with the Least Significant Bit (LSB) being transferred first: the input has an active pull down and requires CMOS logic level inputs; DI will accept data on the falling edge of CLK-signal; see table 2 for input data protocol SPI interface clock input; clocks the shiftregister; CLK has an internal active pull down and requires CMOS logic level inputs 6, 7, 8, 9, GND 20, 21, 22, 23 10 11 12 13 14 15 16 OUTH1 OUTL1 OUTL2 OUTH2 OUTH3 VS CSN 17 DO 18 DI 19 CLK 3 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G 1.3 Pin No. 24 Pin Definitions and Functions (cont'd) Symbol VCC Function Output voltage regulator; 5V logic supply, block to GND with an 100nF external ceramic capacitor directly at the IC + external capacitor CQ 22 F CAN Receive data output; CAN Transmit data input; integrated pull up Pulse width control; for high side switch 1 Oscillator input; time base for power on reset, watchdog window and stand by timer for HS3, to program connect external resistor to GND 25 26 27 28 RxD TxD PWM OSC 4 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G 1.4 Functional Block Diagram OUTL1 Charge Pump Drive OUTL2 Drive Vs Protection + Drive PWM Switch Fail Detect OUTH2 Drive OUTH3 Drive CSN OUTH1 UVLO POR SPI CLK DI DO Vcc + Band Gap Timer Reset Generator + Window Watchdog CAN Standby / Sleep Control OSC RO RTL Fail Management CANH CANL RTH Filter H Output Stage L Output Stage Driver Temp. Protect Input Stage TxD Receiver RxD CAN Fail Detect GND Figure 2 5 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G 1.5 Circuit Description The TLE 6262 G is a monolithic IC, which incorporates a failure tolerant low speed CANtransceiver for differential mode data transmission, a low dropout voltage regulator for internal and external 5V supply as well as a SPI interface to control and monitor the IC. Further there are integrated three high side switches, two low side switches, a window watchdog circuit and a reset circuit. Both, the window watchdog and reset function are referring to a time base that is programmable via an external resistor. Figure 2 shows a block schematic diagram of the TLE 6262 G Table 1: mode truth table Feature VCC Reset Watchdog SPI CAN transmit CAN receive OUTHS 13) 4) 5) OUTHS 23) 5) OUTHS 33) 5) OUTHS3-auto timing3) 5) OUTLS 13) 6) OUTLS 23) 6) 1) 2) 3) 4) 5) 6) normal mode ON ON ON1) ON ON ON ON ON ON OFF ON ON Receive-only mode ON ON ON1) ON OFF ON ON ON ON ON ON ON VBAT stand-by mode ON ON ON1) ON OFF OFF2) ON ON ON ON ON ON at low VCC output current only active when watchdog undercurrent function is not activated a bus wake-up is monitored by setting the RxD output low only active when selected via SPI also active when driven via the PWM input automatically disabled when a reset occurs automatically disabled when a reset or watchdog reset respectively, occurs or the watchdog is disabled by the undercurrent function 6 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G CAN Transceiver The TLE 6262 is optimized for low speed data transmission up to 125 kbaud in automotive applications. Normally a differential signal is transmitted or received respectively. When a bus wiring failure (see table 4) is detected the device automatically switches to a dedicated CANH or CANL single-wire mode to maintain the communication if necessary. Therefore it is equipped with one differential receiver and four single ended comparators (two for each bus line). To avoid false triggering by external RF influences the single wire modes are activated after a certain delay time. As soon as the bus failure disappears the transceiver switches back to differential mode after another time delay. The bus failures are monitored via the diagnosis protocol of the SPI. Therefore it is possible to distinguish 6 CAN bus failures or failure groups on the bits 8 to 13 (see table 3). To reduce EMC caused by the transceiver the dynamic slopes of the CANL and CANH signals are both limited and symmetric. This allows the use of an unshielded twisted or parallel pair of wires for the bus. During single-wire transmission (bus-failure) the EMC performance of the system is degraded from the differential mode. The differential receiver threshold is set to typ. -2.8 V. This ensures correct reception in the normal operation mode as well as in the failure cases 1, 2, 3a and 4 with a noise margin as high as possible. When one of the bus failures 3, 5, 6, 6a, and 7 is detected, the defective bus wire is disabled by switching off the affected bus termination and output stage. The CAN-transceiver offers three different operation modes that are controlled via the SPI: the normal operation mode, Receive-only mode and Vbat stand-by mode. Please see the state diagram (figure 3). In the Vbat stand-by mode the RTL output voltage is switched to VS. In case of a wake-up via the bus lines or one of the bus lines respectively, the TLE 6262 automatically sets the RxD output LOW. To send respectively receive messages the CAN-transceiver can now be set in normal operation mode or receive-only mode by the microcontroller. When a reset occurs the transceiver circuit is automatically switched to Vbat-stand-by mode because the SPI input bits are automatically set LOW for this event. A thermal shutdown of the CAN-transceiver circuit is monitored via the SPI diagnosis bit 15. 7 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G Start Up Power Up Normal Mode NSTB 1 ENT 1 V CC ON NSTB ENT 1 1 ENT 0 ENT 1 NSTB ENT or VCC 0 0 VRT RxD-Only NSTB 1 NSTB 0 NSTB VCC 0 or VRT 1 Vbat Stand-By NSTB 0 ENT 0 VCC ON ENT 0 0 1 V CC ON NSTB NSTB ENT Go- To-Sleep Mode NSTB 0 ENT 1 V CC ON ENT 1 Figure 3: State Diagram Low Dropout Voltage Regulator The TLE 6262 is able to drive external 5V loads up to 45 mA. Its output voltage tolerance is less than 2%. In addition the regulator circuit drives the internal loads like the CANtransceiver circuit. An external reverse current protection is recommended to prevent the output capacitor from being discharged by negative transients or low input voltage. Stability of the output voltage is guaranteed for output capacitors CVCC 100 nF. Nevertheless a lot of applications require a much larger output capacitance to buffer the output voltage in case of low input voltage or negative transients. Furthermore the due function of e.g. the reset and 3V-supervisor circuit are supported by a larger output capacitance because of their reaction times. Therefore a output capacitance CVCC 10 F is recommended. 8 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G SPI (serial peripheral interface) The 16-bit wide programming word or input word (see table 1) is read in via the data input DI, and this is synchronized with the clock input CLK supplied by the C. The diagnosis word appears synchronously at the data output DO (see table 3). The transmission cycle begins when the chip is selected by the chip select not input CSN (H to L). After the CSN input returns from L to H, the word that has been read in becomes the new control word. The DO output switches to tristate status at this point. For details of the SPI timing please refer to figure 3 to 7. Oscillator All internal delay times are referring to the internal oscillator frequency, which is set by an external resistor from pin OSC to GND. The oscillator frequency and the resulting internal cycling time can be calculated by the equations: 28, 45 10 [ HzW ] f OSC = ----------------------------------------R OSC 9 32 t CYL = ----------f OSC Window Watchdog, Reset and 3V-Supervisor When the output voltage VCC exceeds the reset threshold voltage VRT the reset output RO is switched HIGH after a delay time of 16 cycles. This is necessary for a defined start of the microcontroller when the application is switched on. As soon as an under-voltage condition of the output voltage (VCC < VRT) appears, the reset output RO is switched LOW again. The LOW signal is guaranteed down to an output voltage VCC 1V. Please refer to fig.11, reset timing diagram. Should the output voltage fall short of the 3V-supervisor threshold VST an internal flipflop is set LOW. The SPI diagnosis bit 7 monitors this. In normal operation this flip-flop has to be activated via the SPI input bit 7. This feature is useful e.g. to monitor that the RAM data of the microcontroller might be damaged or the application is connected to VS the first time. After the above described delayed reset (LOW to HIGH transition of RO) the window watchdog circuit is started by opening a long open window of 32 cycles. Now the microcontroller has to service a watchdog trigger signal via the SPI interface (input bit 0). A watchdog trigger is detected as a falling edge by sampling for 2 cycles a HIGH followed by 2 cycles LOW of the SPI input bit 0. The long open window ensures a simple and fast 9 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G synchronization of the TLE 6262 watchdog timing to the watchdog services of the microcontroller. After the first trigger the watchdog has to be serviced by meeting an open window of 20 cycles that follows a closed window of 12 cycles. A correct watchdog service immediately results in starting the next closed window. Please refer to fig. 10, watchdog timing diagram. If the trigger signal does not meet the open window (trigger to early or to late) the reset output RO is set LOW for a period of 4 cycles. Afterwards a long open window is started again. In addition, the SPI diagnosis bit 2 is set HIGH to monitor a watchdog reset. Both, the undervoltage reset and the watchdog reset are setting all SPI input bits LOW. To avoid a cyclic wake-up of the microcontroller in low power mode (sleep mode) the watchdog circuit can be automatically disabled at low output currents (ICC < ICCWD). To activate this feature the SPI input bit 8 has to be set HIGH. In this under-current mode the low side switches are switched off automatically by the TLE 6262 to guarantee failsave operation of the application. When the microcontroller returns back to normal mode (ICC > ICCWD) the first closed window is transformed to an open window so that the total open window time is 32 cycles. This ensures a more simple and fast synchronization of the TLE 6262 watchdog timing to the watchdog services of the microcontroller. Flash program mode To disable the watchdog feature a flash program mode is available. This mode is selected by applying a voltage of 6.8V < VPWM < 7.2V at pin PWM. This is useful e.g. if the flash-memory of the micro has to be programmed and therefore a regular watchdog triggering is not possible. If the SPI is required in the flash program mode to change e.g. the mode of the TLE6262 the first input telegram has to be "00000000". High Side Switch 1 The high side output OUTH1 is able to switch loads up to 250 mA. Its on-resistance is 1.0 W typ. @ 25C. This switch can be controlled either via the PWM input or the SPI input bit 1. When the input PWM is used it has to be enabled by setting the SPI input bit 11 HIGH. In case of both control inputs being active the PWM signal is masked by the SPI signal (see fig. 8, High Side Switch 1 Timing Diagram). The SPI diagnosis bit 14 monitors a thermal shutdown of the switches, whereas bit 0 flags a thermal prewarning. By this the microcontroller is able to reduce the power dissipation of the TLE 6262 by switching off functions of minor priority before the temperature threshold of the thermal shutdown is reached. Further OUTH1 is protected against short circuit and overload. The SPI diagnosis bit 1 indicates an overload of OUTH1. As soon as the under-voltage condition of the supply voltage is met (VS < VUVOFF), the switches are automatically disabled by the under-voltage lockout circuit. 10 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G This is flagged by the SPI diagnosis bit 3. Moreover the switches are disabled when a reset occurs. High Side Switch 2 The high side output OUTH2 is able to switch loads up to 250 mA. Its on-resistance is 1.0 W typ. @ 25C. This switch is controlled via the SPI input bit 2. The SPI diagnosis bit 14 monitors a thermal shutdown of the switches, whereas bit 0 flags a thermal prewarning. By this the microcontroller is able to reduce the power dissipation of the TLE 6262 by switching off functions of minor priority before the temperature threshold of the thermal shutdown is reached. As soon as the under-voltage condition of the supply voltage is met (VS < VUVOFF), the switches are automatically disabled by the under-voltage lockout circuit. This is flagged by the SPI diagnosis bit 3. Moreover the switches are disabled when a reset occurs. High Side Switch 3 The high side output OUTH3 is able to switch loads up to 150 mA. Its on-resistance is 1.5 W typ. @ 25C. This switch is controlled via the SPI input bits 3 and 4. To supply external wake-up circuits in low power mode (sleep mode or Vbat-stand-by mode), the output OUTH3 can be periodically activated by the internal oscillator circuit. For activating this feature the SPI input bits 3 and 4 have to be set HIGH. The autotiming period is 128 internal cycle times; the on-time is 2 cycles. In case of a watchdog reset the autotiming period may be shorter. The SPI diagnosis bit 14 monitors a thermal shutdown of the switches, whereas bit 0 flags a thermal prewarning. By this the microcontroller is able to reduce the power dissipation of the TLE 6262 by switching off functions of minor priority before the temperature threshold of the thermal shutdown is reached. As soon as the under-voltage condition of the supply voltage is met (VS < VUVOFF), the switches are automatically disabled by the under-voltage lockout circuit. This is flagged by the SPI diagnosis bit 3. Moreover the switches are disabled when a reset occurs. Low Side Switches 1/2 The two low side outputs OUTL1 and OUTL2 are able to switch loads up to 100 mA. Their on-resistance is 1.5 W (typ.) @ 25C. This switches are controlled via the SPI input bits 5 and 6. In case of high inrush currents a built in zener circuit (typ. 37 V) activates the switches to protect them. The SPI diagnosis bit 14 monitors a thermal shutdown of the switches, whereas bit 0 flags a thermal prewarning. By this the microcontroller is able to reduce the power dissipation of the TLE 6262 by switching off functions of minor priority before the temperature threshold of the thermal shutdown is reached. The SPI diagnosis bits 5/6 11 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G are giving a feedback about current status of OUTL1/OUTL2. As soon as the undervoltage condition of the supply voltage is met (VS < VUVOFF), the switches are automatically disabled by the under-voltage lockout circuit. This is flagged by the SPI diagnosis bit 3. In addition the outputs OUTL1 and OUTL2 are also disabled when the watchdog is switched off in undercurrent state or when a reset occurs. 12 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G Table 2 Input Data Protocol BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H = ON L = OFF not used not used not used not used PWM Enable CAN Enable Transmit CAN Not Stand-By Watchdog Control Supervisor Enable LS-Switch 2 LS-Switch 1 HS3 Auto Timing HS-Switch 3 HS-Switch 2 HS-Switch 1 Watchdog Trigger Table 3 Diagnosis Data Protocol BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H = ON L = OFF Thermal Shutdown Transceiver Thermal Shutdown Switches CAN Failure 2 and 4 CAN Failure 1 and 3a CAN Failure 6 CAN Failure 6a CAN Failure 6a, 5 and 7 CAN Failure 3 Vcc < 3V Status LS2 Status LS1 not used Vs Undervoltage Lockout Window Watchdog Reset Overload HS1 Temperature Prewarning 13 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G Table 4 CAN bus line failure cases (according to ISO 11519-2) failure # 1 2 3 4 5 6 7 failure description CANL line interrupted CANH line interrupted CANL shorted to Vbat, CANL > 7.2 V CANH shorted to GND CANL shorted to GND CANH shorted to Vbat; CANH > 7.2 V CANL shorted to CANH 3a (no ISO failure) CANL shorted to Vcc; 3.2 V < CANL < 7.2 V 6a (no ISO failure) CANH shorted to Vcc; 1.8 V < CANH < 7.2 V 14 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G 2 2.1 Electrical Characteristics Absolute Maximum Ratings Symbol Limit Values min. max. Unit Remarks Parameter Voltages Supply voltage Supply voltage Regulator output voltage CAN input voltage (CANH, CANL) CAN input voltage (CANH, CANL) VS VS VCC VCANH/L VCANH/L -0.3 -0.3 -0.3 -10 -40 -0.3 28 40 5.5 28 40 V V V V V V V V V V - tp< 0.5s; tp/T < 0.1 VS >0 V tp< 0.5s; tp/T < 0.1 0 V < VS < 24 V 0 V < VCC < 5.5 V 0 V < VS < 24 V 0 V < VCC < 5.5 V 0 V < VS < 24 V 0 V < VCC < 5.5 V human body model; C = 100pF, R = 1.5kW human body model; C = 100pF, R = 1.5kW Logic input voltages (DI, CLK, VI CSN, OSC, PWM, TxD) Logic output voltage (DO, RO, RxD) Termination input voltage (RTH, RTL) Electrostatic discharge voltage at pin CANH, CANL Electrostatic discharge voltage Currents Output current; Vcc Output current; OUTH1 Output current; OUTH2 Output current; OUTH3 Output current; OUTL1 Output current; OUTL2 VCC +0.3 VDO/RO/RD -0.3 VTL /TH VESD VESD -0.3 -4000 -2000 VCC +0.3 VS +0.3 4000 2000 ICC IOUTH1 IOUTH2 IOUTH3 IOUTL1 IOUTL2 - *) -0.7 -0.5 -0.2 -0.2 - 0.3 0.3 0.2 0.4 0.4 A A A A A A internally limited *) internally limited tp< 0.5s; tp/T < 0.1 tp< 0.5s; tp/T < 0.1 tp< 0.5s; tp/T < 0.1 tp< 0.5s; tp/T < 0.1 15 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G 2.1 Absolute Maximum Ratings (cont'd) Symbol Limit Values min. max. Unit Remarks Parameter Temperatures Junction temperature Storage temperature Tj Tstg -40 -50 150 150 C C - - Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. 16 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G 2.2 Operating Range Symbol Limit Values min. max. V V/ms After VS rising above VUV ON - Outputs in tristate Outputs in tristate - Parameter Supply voltage Supply voltage slew rate Supply voltage increasing Supply voltage decreasing Logic input voltage (DI, CLK, CSN, PWM, TxD) Output current Output current Output capacitor SPI clock frequency OSC-Adjust Resistor Junction temperature Thermal Resistances Junction pin Junction ambient Unit Remarks VS dVS /dt VUV OFF 27 -0.5 -0.3 -0.3 -0.3 5 VS VS VI ICC ICC CCC fCLK ROSC Tj VUV ON V VUV OFF V VCC V 35 45 mA mA mF 1 680 150 MHz kW C T < 0.1s 22 - 51 -40 - Ta=-40C; f = 10kHz - Rthj-pin Rthj-a - - 25 65 K/W K/W measured to pin 7 - Thermal Prewarning and Shutdown (junction temperatures) Thermal prewarning ON temperature Thermal shutdown temp. Ratio of SD to PW temp. TjPW TjSD 120 150 135 170 200 - 160 C C - C bit 0 of SPI diagnosis word; hysteresis 30K (typ.) hysteresis 30K (typ.) - hysteresis 10K (typ.) TjSD / TjPW 1.05 Thermal shutdown temp. CAN TjSD 17 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G 2.3 Electrical Characteristics 9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; CANtransceiver circuitry: - 40 C < Tj < 125 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values min. typ. max. Unit Test Condition Quiescent current Pin VS Current consumption Quiescent current ISSB1 = IS - ICC Voltage Regulator; Pin VCC Output voltage Output voltage Line regulation Load regulation IS ISSB1 - - 5 180 10 280 mA mA low power mode; VS=12V; Tj=25C VCC VCC ,VCC ,VCC 4.9 4.8 -20 -25 5.0 5.0 5.2 5.5 20 25 V V mV mV dB mA 0.1mA < ICC< 30mA 0A < ICC < 100A 9 V < VS < 15 V; ICC = 10mA 0.1mA < ICC< 30mA; VS = 9V VS < 1 Vss; CQ 22F; 100Hz< f <100kHz 1) ICC = 30 mA; see note 1) Power supply ripple rejection PSRR Output current limit Drop voltage 40 45 60 0.15 0.45 VDR = VS - VCC Oscillator; Pin OSC Oscillating frequency Internal cycling time (1/32 * fOSC)-1 ICCmax VDR V fOSC tCYL 62.8 383 509 637 kHz s ROSC = 453kW ROSC = 453kW 1) measured when the output voltage VCC has dropped 100 mV from the nominal value obtained at 13.5 V input voltage VS 18 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G 2.3 Electrical Characteristics (cont'd) 9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; CANtransceiver circuitry: - 40 C < Tj < 125 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values min. typ. max. Unit Test Condition Reset Generator; Pin RO Reset threshold voltage Reset low output voltage VRT VRO 4.0 4.3 0.2 4.65 0.4 V V IRO = 1mA (VCC VRT) or VCC 1V (IRO = 200 A) Reset high output voltage Reset pull up current Reset reaction time Reset delay time (16 cyl.) VRO IRO tRR tRD 4.0 20 1 6.1 150 3 8.1 VCC+ V 0.1 500 10 10.2 mA s ms VRO = 0V VCC < VRT to RO = L ROSC = 453kW 3 V Supervisor; (bit 7 of SPI diagnosis word) Supervisor threshold voltage VST Supervisor reaction time 2.3 2 2.7 8 3.1 20 V s VCC < VST to diagnosis bit 7 = L tSR Watchdog Generator tWD Closed window time (12 cyl.) tCW Open window time (20 cyl.) tOW Watchdog reset-puls time tWDR Watchdog trigger time (4 cyl.) Watchdog activating current 7.6 4.6 7.7 1.5 2 10 6.1 10.2 2.0 4 12.3 7.6 12.7 2.6 12 ms ms ms ms mA ROSC = 453kW ROSC = 453kW ROSC = 453kW ROSC = 453kW Tj < 85 C; Watchdog OFF when ICC < ICCWD and SPIinput bit 8 = H ICCWD Watchdog activating current hysteresis ICCWDhys 0.5 mA 19 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G 2.3 Electrical Characteristics (cont'd) 9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; CANtransceiver circuitry: - 40 C < Tj < 125 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Long open window (32 cyl.) Symbol Limit Values min. typ. 16.2 max. 20.4 12.2 Unit Test Condition ms ROSC = 453kW sleep mode (WD OFF) to normal mode ICCWDhys Switches Under-Voltage Lockout (bit 3 of SPI diagnosis word) UV-Switch-ON voltage UV-Switch-OFF voltage UV-ON/OFF-Hysteresis VUV ON VUV OFF VUV HY - 4.50 - 5.35 4.85 0.5 6.00 5.20 - V V V VS increasing VS decreasing VUV ON - VUV OFF High Side Output OUTH1; (controlled by PWM or bit 1 of SPI input word) Static Drain-Source ON-Resistance; IOUTH1 = -0.25 A Active zener voltage RDSON H1 - 1.0 1.5 2.0 4.0 -0.5 1 - 100 100 -0.3 50 -0.5 W W V V A ms ms A ms A 5.2 V VS 9 V IOUTH1 = - 0.25 A IOUTH1 = 0.25 A VOUTH1 = 0 V PWM to OUTH1; RL = 100 W PWM to OUTH1; RL = 100 W - VOUTH1 Clamp diode forward voltage VOUTH1 Leakage current IOLH1 Switch ON delay time tdONH1 Switch OFF delay time Overcurrent shutdown threshold Shutdown delay time Current limit -5.0 -100 -3.0 0.8 -5 10 20 tdOFFH1 ISDH1 tdSDH1 IOCLH1 -1.0 10 -2.0 -0.6 25 -1.0 20 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G 2.3 Electrical Characteristics (cont'd) 9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; CANtransceiver circuitry: - 40 C < Tj < 125 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values min. typ. max. Unit Test Condition PWM Input to control OUTH1; Pin PWM (high active) H-input voltage threshold L-input voltage threshold Hysteresis of input voltage Pull down current Input capacitance VIH VIL VIHY II CI - 0.2 Vcc 50 5 - - - 200 25 10 0.7 VCC - 500 180 15 V V mV mA pF - - - VI = 0.2 * VCC 0 V < VCC < 5.25 V High Side Output OUTH2; (controlled by bit 2 of SPI input word) Static Drain-Source ON-Resistance; IOUTH2 = -0.25 A Active zener voltage RDSON H2 - 1.0 1.5 2.0 4.0 -0.5 1 - 100 100 W W V V A s s 5.2 V VS 9 V IOUTH2 = - 0.25 A IOUTH2 = 0.25 A VOUTH2 = 0 V CSN high to OUTH2; RL = 100 W CSN high to OUTH2; RL = 100 W VOUTH2 Clamp diode forward voltage VOUTH2 Leakage current IOLH1 Switch ON delay time tdONH1 Switch OFF delay time -5.0 -100 -3.0 0.8 -5 10 20 tdOFFH1 High Side Output OUTH3; (controlled by bit 3 and bit 4 of SPI input word) Static Drain-Source ON-Resistance; IOUTH3 = -0.15 A Active zener voltage RDSON H3 - 1.5 2.0 3.0 5.0 -0.5 1 - W W V V A 5.2 V VS 9 V IOUTH3 = - 0.15 A IOUTH3 = 0.15 A VOUTH3 = 0 V VOUTH3 Clamp diode forward voltage VOUTH3 Leakage current IOLH3 -5.0 -100 -3.0 0.8 -5 21 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G 2.3 Electrical Characteristics (cont'd) 9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; CANtransceiver circuitry: - 40 C < Tj < 125 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Leakage current Switch ON delay time Switch OFF delay time Auto time period (128 cyl.) Auto time ON duty cycle (2 cyl.) Symbol Limit Values min. typ. 5 10 20 49 65 1/64 100 100 82 max. - Unit Test Condition A s s ms VOUTH3 = 5 V CSN high to OUTH3; RL = 100 W CSN high to OUTH3; RL = 100 W ROSC = 453kW; SPI-bit 4 = H, no WD reset referring to tPH3 IOLH3 tdONH3 tdOFFH3 tPH3 D.C. Low Side Output OUTL1 (bit 5 of SPI input word) Static Drain-Source ON-Resistance; IOUTL1 = 0.1 A Active zener clamp voltage Leakage current Switch ON delay time Switch OFF delay time RDSON L1 - 1.5 2.0 3.0 5.0 42 5 W W V A s s 5.2 V VS 9 V IOUTL1 = - 0.1 A VOUTL1 =15 V; Tj < 85C CSN high to OUTL1; RL = 100 W CSN high to OUTL1; RL = 100 W VOUTL1 IOLL1 tdONL1 tdOFFL1 32 37 5 5 50 50 Low Side Output OUTL2 (bit 6 of SPI input word) Static Drain-Source ON-Resistance; IOUTL2 = 0.1 A Active zener clamp voltage Leakage current Switch ON delay time Switch OFF delay time RDSON L2 - 1.5 2.0 3.0 5.0 42 5 W W V A s s 5.2 V VS 9 V IOUTL2 = - 0.1 A VOUTL2 =15 V; Tj < 85C CSN high to OUTL2; RL = 100 W CSN high to OUTL2; RL = 100 W VOUTL2 IOLL2 tdONL2 tdOFFL2 32 37 5 5 22 50 50 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G 2.3 Electrical Characteristics (cont'd) 9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; CANtransceiver circuitry: - 40 C < Tj < 125 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values min. typ. max. Unit Test Condition CAN-Transceiver Receiver Output RD HIGH level output voltage LOW level output voltage Transmission Input TD HIGH level input voltage threshold LOW level input voltage threshold HIGH level input current LOW level input current Bus Lines CANL, CANH Differential receiver recessive-to-dominant threshold voltage Differential receiver dominant-to-recessive threshold voltage CANH recessive output voltage CANL recessive output voltage CANH dominant output voltage VOH VOL VCC - 0.9 0 - - VCC 0.9 V V I0 = - 250A I0 = 1.25mA VIH VIL IIH IIL 0.52 0.70 V VCC 0.30 0.48 VCC V -10 -40 VCC -140 -600 VCC -40 -200 A A Vi = 4 V Vi = 1 V VdRxD(rd) -2.8 -2.5 -2.2 V VdRxD(dr) -3.1 -2.9 -2.5 V VCANHr VCANLr VCANHd 0.1 0.2 - 0.3 - V V V TxD = VCC; RRTH < 4 kW TxD = VCC; RRTL < 4 kW TxD = 0 V; ICANH = - 40 mA VCC - 0.2 VCC -1.4 VCC -1.0 VCC 23 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G 2.3 Electrical Characteristics (cont'd) 9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; CANtransceiver circuitry: - 40 C < Tj < 125 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter CANL dominant output voltage CANH output current Symbol Limit Values min. typ. 1.0 -80 0 80 0 7.3 Unit Test Condition V mA A mA A V TxD = 0 V; ICANL = 40 mA VCANH = 0 V; TxD = 0 V sleep mode; VCANH = 12 V VCANL = 5 V; TxD = 0 V sleep mode; VCANL = 0 V; VS = 0 V normal operation mode max. 1.4 -50 5 110 5 8.0 VCANLd ICANH - -110 -5 CANL output current ICANL 50 -5 Voltage detection threshold Vdet(th) for short-circuit to battery voltage on CANH and CANL CANH wake-up voltage threshold CANL wake-up voltage threshold 6.5 VWAKEH VWAKEL 1.2 2.2 1.6 2.4 -5 -5 1.9 3.1 2.1 3.0 0 0 2.7 3.9 2.6 3.4 5 5 V V V V A A - - CANH single-ended receiver VCANH threshold CANL single-ended receiver threshold CANL leakage current CANH leakage current failure cases 3, 5 and 7 failure case 6 and 6a VCANL ICANLl ICANHl VCC = 0 V, VS = 0 V, VCANL = 13.5 V, Tj < 85 C VCC = 0 V;VS = 0 V; VCANH = 5 V; Tj < 85 C Termination Outputs RTL, RTH RTL to VCC switch-on resistance RTL to BAT switch series resistance RRTL RoRTL - 5 40 15 95 30 W kW Io = - 10 mA; VBAT-stand-by 24 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G 2.3 Electrical Characteristics (cont'd) 9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; CANtransceiver circuitry: - 40 C < Tj < 125 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter RTH to ground switch-on resistance RTH output voltage RTH pull-down current RTL pull-up current Symbol Limit Values min. typ. 40 0.7 75 -75 Unit Test Condition W V A A Io = 10 mA Io = 1 mA; Vbat-stand-by mode failure cases 6 and 6a failure cases 3, 3a, 5 and 7 max. 95 1.0 120 -40 RRTH VoRTH IRTHpd IRTLpu - - 40 -120 25 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G 2.3 Electrical Characteristics (cont'd) 9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; CANtransceiver circuitry: - 40 C < Tj < 125 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values min. typ. max. Unit Test Condition CAN-Transceiver Dynamic Characteristics CANH and CANL bus output trd transition time recessive-todominant CANH and CANL bus output tdr transition time dominant-torecessive Minimum dominant time for wake-up on CANL or CANH Failure cases 3 and 6 detection time Failure case 6a detection time Failure cases 5, 6, 6a and 7 recovery time Failure cases 3 recovery time Failure cases 5 and 7 detection time Failure cases 5 detection time Failure cases 6, 6a and 7 detection time Failure cases 5, 6, 6a and 7 recovery time 0.6 1.2 2.1 s 10% to 90%; C1 = 10 nF; C2 = 0; R1 = 100 W 10% to 90%; C1 = 1 nF; C2 = 0; R1 = 100 W stand-by mode; VS = 13.5 V 0.3 0.6 1.3 s twu(min) tfail 12 30 2.0 30 250 1.0 20 45 4.8 45 500 2.0 1.0 4.0 1.0 38 80 8.0 80 750 4.0 2.4 8.0 2.4 s s ms s s ms ms ms stand-by modes; VS = 13.5 V stand-by modes; VS = 13.5 V stand-by modes; VS = 13.5 V tfail 0.4 0.8 0.4 s 26 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G 2.3 Electrical Characteristics (cont'd) 9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; CANtransceiver circuitry: - 40 C < Tj < 125 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol - Limit Values min. typ. 1.5 Unit Test Condition s C1 = 100 pF; C2 = 0; R1 = 100 W; no failures and bus failure cases 1, 2, 3a and 4 C1 = C2 = 3.3 nF; R1 = 100 W; no bus failure and failure cases 1, 2, 3a and 4 C1 100 pF; C2 = 0; R1 = 100 W; bus failure cases 3, 5, 6, 6a and 7 C1 = C2 = 3.3 nF; R1 =100 W; bus failure cases 3, 5, 6, 6a and 7 C1 = 100 pF; C2 = 0; R1 =100 W; no failures and bus failure cases 1, 2, 3a and 4 C1 = C2 = 3.3 nF; R1 = 100 W; no bus failure and failure cases 1, 2, 3a and 4 C1 100 pF; C2 = 0; R1 = 100 W; bus failure cases 3, 5, 6, 6a and 7 C1 = C2 = 3.3 nF; R1 = 100 W; bus failure cases 3, 5, 6, 6a and 7 max. 2.1 Propagation delay tPD(L) TxD-to-RxD LOW (recessive to dominant) - 1.7 2.4 s - - Propagation delay tPD(H) TxD-to-RxD HIGH (dominant to recessive) - 1.8 2.0 1.5 2.5 2.6 2.0 s s s - 2.5 3.5 s - - ne Edge-count difference (falling edge) between CANH and CANL for failure cases 1, 2, 3a and 4 detection Edge-count difference (rising edge) between CANH and CANL for failure cases 1, 2, 3a and 4 recovery TxD permanent dominant disable time - 1.0 1.5 4 2.1 2.6 - s s - - 2 - - tTxD 1.3 2.0 3.5 ms 27 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G 2.3 Electrical Characteristics (cont'd) 9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; CANtransceiver circuitry: - 40 C < Tj < 125 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values min. typ. max. Unit Test Condition SPI-Interface Logic Inputs DI, CLK and CSN H-input voltage threshold L-input voltage threshold Hysteresis of input voltage Pull up current at pin CSN Pull down current at pin DI and CLK Input capacitance at pin CSN, DI or CLK Logic Output DO H-output voltage level L-output voltage level Tri-state leakage current Tri-state input capacitance VIH VIL VIHY IICSN IICLK/DI CI - 0.3 * - - 200 -25 25 10 0.7 * V V mV mA mA pF - VCC - 500 -5 100 15 - VCC 50 -100 5 - - VCSN = 0.7 VCC VDI = 0.2 VCC 0 V < VCC < 5.25 V VDOH VDOL IDOLK CDO VCC - -10 - VCC 0.2 - 10 - 0.4 10 15 V V mA pF IDOH = 1 mA IDOL = - 1.6 mA VCSN = VCC 0 V < VDO < VCC VCSN = VCC 0 V < VCC < 5.25 V - 1.0 - 0.7 Data Input Timing Clock period Clock high time Clock low time Clock low before CSN low tpCLK tCLKH tCLKL tbef 1000 500 500 500 28 - - - - - - - - ns ns ns ns - - - - version: 2.03 date: 2002-03-20 Final Data TLE 6262 G 2.3 Electrical Characteristics (cont'd) 9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; CANtransceiver circuitry: - 40 C < Tj < 125 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter CSN setup time CLK setup time Clock low after CSN high DI setup time DI hold time Input signal rise time at pin DI, CLK and CSN Input signal fall time at pin DI, CLK and CSN Data Output Timing DO rise time DO fall time DO enable time DO disable time DO valid time Symbol Limit Values min. typ. - - - - - - - max. - - - - - 200 200 500 500 500 250 250 - - Unit Test Condition ns ns ns ns ns ns ns - - - - - - tlead tlag tbeh tDISU tDIHO trIN tfIN - trDO tfDO tENDO tDISDO tVADO - - - - - 50 50 - - 100 100 100 250 250 250 ns ns ns ns ns CL = 100 pF CL = 100 pF low impedance high impedance VDO < 0.2 VCC; VDO > 0.7VCC; CL = 100 pF 29 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G 3 Timing Diagrams CSN High to Low & rising edge of CLK: DO is enabled. Status information is transfered to Output Shift Register CSN time CSN Low to High: Data from Shift-Register is transfered to Output Power Switches CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 actual Data DI 0 1 2 3 4 5 _ 6 7 8 9 10 11 12 13 14 15 new Data 0 + 1 + DI: Data will be accepted on the falling edge of CLK-Signal previous Status DO _ 0 _ 1 _ 2 _ 3 _ 4 _ 5 _ 6 _ 7 _ 8 _ 9 ___ 10 11 12 ___ 13 14 15 actual Status 0 1 DO: State will change on the rising edge of CLK-Signal eg. HS1 old Data actual Data Figure 4 Data Transfer Timing 30 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G Figure 5 SPI-Input Timing Figure 6 Turn OFF/ON Time 31 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G Figure 7 DO Valid Data Delay Time and Valid Time Figure 8 DO Enable and Disable Time 32 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G Figure 9: High Side Switch1 Timing Diagram SPI input bit 1 H L PWM (SPI input bit 11 = H) t H L HSSwitch1 t ON OFF t 33 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G Figure 10: Watchdog Time-out Definitions tWD tCW closed window tOW open window t / ms Figure 11: Watchdog Timing Diagram tCW WD Trigger tLOW tOW tCW+tOW tLOW tLOW tCW tOW tCW tLOW tCW tOW Reset Out tWDR t Watchdog timer reset t normal operation timeout (to long) normal operation timeout (to short) normal operation 34 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G Figure 12: Reset Timing Diagram Vcc VRT VST t < tRR WD Trigger tRD tLOW tLOW tCW tOW tCW tRD tLOW tCW t Reset Out tWDR tRR t Watchdog timer reset t SPI diagnosis bit 7 start up HIGH normal operation tSR undervoltage start up LOW activation by microcontroller t 35 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G 4 Application Vbat CAN bus +VS CSN CLK 22 F 68 nF DI CANH CANL TxD RxD RTH PWM RTL RQ OUTL2 OUTL1 OUTH3 OUTH2 OSC OUTH1 GND 453 k9 22 F DQ P Vcc GND TLE 6262 G Figure 13 Application Circuit 36 version: 2.03 date: 2002-03-20 Final Data TLE 6262 G 5 Package Outlines P-DSO-28-6 (Plastic Dual Small Outline Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". Dimensions in mm 37 version: 2.03 date: 2002-03-20 GPS05123 Final Data TLE 6262 G Edition 1999-10-12 Published by Infineon Technologies AG St.-Martin-Strasse 53 D-81541 Munchen (c) Infineon Technologies AG1999 All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. 38 version: 2.03 date: 2002-03-20 |
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